High-performance and low-voltage sense-amplifier techniques for sub-90nm SRAM

被引：26

作者：

Sinha, M ^{[1
]}

Hsu, S ^{[1
]}

Alvandpour, A ^{[1
]}

Burleson, W ^{[1
]}

Krishnamurthy, R ^{[1
]}

Borkar, S ^{[1
]}

机构：

[1] Univ Massachusetts, Dept Elect & Comp Engn, Amherst, MA 01003 USA

来源：

IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS | 2003年

关键词：

D O I：

10.1109/SOC.2003.1241474

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Large bit-line capacitance is one of the main bottlenecks to the performance of on-chip caches. New sense amplifier techniques need to explicitly address this challenge. This paper describes two sensing techniques to overcome this problem: a current sense amplifier (CSA) and a charge transfer sense amplifier (CTSA) and their implementation based on 90nm CMOS technology. The current sense amplifier senses the cell current directly and shows a speed improvement of 17-20% for 128 memory cells as compared to the conventional voltage mode sense amplifier, for same energy. The other is a charge transfer sense amplifier that takes advantage of large bit-line capacitance for its operation. CTSA shows an improvement of 18-22% for read delay for 128 memory cells and consumes 15-18% less energy than the voltage mode sense amplifier. CTSA results in reduced bit-line swing and which in turn leads to 30% lower bit-line energy than the conventional voltage mode.

引用

页码：113 / 116

页数：4

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