An FPGA based open source Network-on-Chip architecture

被引：14

作者：

Ehliar, Andreas ^{[1
]}

Liu, Dake ^{[1
]}

机构：

[1] Linkoping Univ, Dept Elect Engn, S-58183 Linkoping, Sweden

来源：

2007 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, VOLS 1 AND 2 | 2007年

关键词：

D O I：

10.1109/FPL.2007.4380772

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

Networks on Chip (NoC) has long been seen as a potential solution to the problems encountered when implementing large digital hardware designs. In this paper we describe an open source FPGA based NoC architecture with low area overhead, high throughput and low latency compared to other published works. The architecture has been optimized for Xilinx FPGAs and the NoC is capable of operating at a frequency of 260 MHz in a Virtex-4 FPGA. We have also developed a bridge so that generic Wishbone bus compatible IP blocks can be connected to the NoC.

引用

页码：800 / 803

页数：4

共 50 条

[1] Parameterizable Ethernet Network-on-Chip Architecture on FPGA
da Cunha Junior, Helio Fernandes
Silva, Bruno de Abreu
Bonato, Vanderlei
[J]. 2015 EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD), 2015, : 263 - 266
[2] FPGA BASED DESIGN AND ARCHITECTURE OF NETWORK-ON-CHIP ROUTER FOR EFFICIENT DATA PROPAGATION
Krutthika, Hirebasur Krishnappa
Aswatha, Anur Rangappa
[J]. IIOAB JOURNAL, 2020, 11 : 17 - 25
[3] CDMA-BASED network-on-chip architecture
Kim, DW
Kim, MH
Sobelman, GE
[J]. PROCEEDINGS OF THE 2004 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1 AND 2: SOC DESIGN FOR UBIQUITOUS INFORMATION TECHNOLOGY, 2004, : 137 - 140
[4] Expansible Network-on-Chip Architecture
Pedroso Pires, Ivan Luiz
Zanata Alves, Marco Antonio
Pessoa Albini, Luiz Carlos
[J]. ADVANCES IN ELECTRICAL AND COMPUTER ENGINEERING, 2018, 18 (02) : 61 - 68
[5] A Code Partitioning Tool for Simulink Models to Implement on FPGA-based Network-on-Chip Architecture
Miyasono, Satoru
Moriai, Yosuke
Saito, Hiroshi
[J]. 2014 IEEE 8TH INTERNATIONAL SYMPOSIUM ON EMBEDDED MULTICORE/MANYCORE SOCS (MCSOC), 2014, : 141 - 148
[6] A Scalable and Low-Power FPGA-Aware Network-on-Chip Architecture
Mazumdar, Somnath
Scionti, Alberto
Portero, Antoni
Martinovic, Jan
Terzo, Olivier
[J]. COMPLEX, INTELLIGENT, AND SOFTWARE INTENSIVE SYSTEMS, CISIS-2017, 2018, 611 : 407 - 420
[7] Fault Tolerant Mesh based Network-on-Chip Architecture
Chatterjee, Navonil
Chattopadhyay, Santanu
[J]. 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2015, : 417 - 420
[8] An Efficient Embryonic Hardware Architecture based on Network-on-Chip
Khalil, Kasem
Eldash, Omar
Dey, Bappaditya
Kumar, Ashok
Bayoumi, Magdy
[J]. 2021 IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2021, : 449 - 452
[9] The Design of a Network-On-Chip Architecture Based On An Avionic Protocol
Ben Achballah, Ahmed
Ben Saoud, Slim
[J]. 2014 WORLD SYMPOSIUM ON COMPUTER APPLICATIONS & RESEARCH (WSCAR), 2014,
[10] PANACA: An Open-Source Configurable Network-on-Chip Simulation Platform
Haase, Julian
Gross, Alexander
Feichter, Maximilian
Goehringer, Diana
[J]. 2022 35TH SBC/SBMICRO/IEEE/ACM SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN (SBCCI 2022), 2022,

← 1 2 3 4 5 →