Heterogeneous high performance computer emulation of a space based radar on-board processor

This paper presents the successful emulation of an on-board processor (OBP) to support Space Based Radar (SBR). The emulation is demonstrated on the forty-eight node dual Xeon Heterogeneous High Performance Computer (HHPC) operated by the Air Force Research Laboratory (AFRL) located in Rome, New York. Each node in the HHPC supports one Annapolis Wildstar II board, composed of 2 Xilinx Virtex II 6 Million gate Field Programmable Gate Arrays (FPGAs). As system complexity increases, debugging the software of tera-scale systems with hundreds to thousands of processors is poorly supported by time consuming simulations. However, the advent of large FPGAs allows a powerful new tool to assist in the architecture development effort-emulation. For the case at hand, the 96 FPGAs of the HHPC are capable of emulating at 8% of the actual system clock speed (20 MHz of 250 MHz) and close to 15% of the 2560 individual processors of the proposed SBR system. Even at this reduced scale, this emulation provides a testing environment roughly a million times more capable than HPC-based simulation for early software bug detection and correction. Further, this framework allows for experimenting with architecture enhancements and changes, and ultimately will ensure a low cost, reliable, fully reprogrammable product produced without re-spins. The embedded system architecture of this SBR OBP is based on AFRL's dual processor, power efficient, programmable, Wafer Scale Signal Processor (WSSP). Target tracking and discrimination algorithms were developed and demonstrated on an earlier 96 processor embodiment of this architecture. For SBR, the algorithm set is being extended to include Synthetic Aperture Radar (SAR) image formation and Moving Target Indication (MTI) algorithms.