Efficient Implementations of Multiple Bit Burst Error Correction for Memories

Soft error induced by space radiation particles can cause serious threat for memories that are widely used in the electronic system of aerospace task. This can corrupt the stored data and cause the system failure. Error correction codes (ECCs) as a system-level radiation hardened method are commonly applied to protect the memories. With the development in process technology, the memory cell becomes smaller and the density increases. One radiation event can include more memory cells leading to multiple bit upset (MBUs). In this case, more advanced ECC such as matrix codes are used to ensure the data correction. However, as the correction ability enhanced, the overhead caused by the parity bits also increases. In this paper, a scheme that interleaves the simple x-bit burst error codes is presented. It not only has more advanced correction ability up to 6-bit or 12-bit burst error correction, but also has lower redundancy. The result shows that the implementation for MBUs is efficient but at the cost of a little decoding delay increase that is tolerant in some applications,