A 10 Gbps SerDes For Wireless Chip-to-chip Communication

This paper presents a 10 Gbps serializer/deserializer (SerDes) with a phase interpolator (PI) based clock and data recovery (CDR) circuit for high-speed and short-range wireless chip-to-chip communication. The SerDes performs 4:1 muxing and 1:4 demuxing functions. The PI-based CDR uses an 8-phase delay-locked loop (DLL) to produce a set of evenly spaced reference clock phases. The phase vernier, then transforms the 8-phases to sampling clocks for the sampler, which performs 2x oversampling to recover the data from the input signal. Implemented in a 65 nm CMOS process, the proposed SerDes achieves a data rate of 10 Gbps and a recovered peak-to-peak clock jitter of 36.25 ps. The 10 Gbps SerDes occupies an active area of 0.095mm(2) and dissipates 88 mW.