A 10 Gbps SerDes For Wireless Chip-to-chip Communication

被引:0
|
作者
Han, Sangwoo [1 ]
Kim, Taegyu [1 ]
Kim, Jintae [2 ]
Kim, Jongsun [1 ]
机构
[1] Konkuk Univ, Elect Engn, Seoul, South Korea
[2] Hongik Univ, Sch Elect & Elect Engn, Seoul, South Korea
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents a 10 Gbps serializer/deserializer (SerDes) with a phase interpolator (PI) based clock and data recovery (CDR) circuit for high-speed and short-range wireless chip-to-chip communication. The SerDes performs 4:1 muxing and 1:4 demuxing functions. The PI-based CDR uses an 8-phase delay-locked loop (DLL) to produce a set of evenly spaced reference clock phases. The phase vernier, then transforms the 8-phases to sampling clocks for the sampler, which performs 2x oversampling to recover the data from the input signal. Implemented in a 65 nm CMOS process, the proposed SerDes achieves a data rate of 10 Gbps and a recovered peak-to-peak clock jitter of 36.25 ps. The 10 Gbps SerDes occupies an active area of 0.095mm(2) and dissipates 88 mW.
引用
收藏
页码:17 / 18
页数:2
相关论文
共 50 条
  • [1] Design and Modeling for Chip-to-Chip Communication at 20 Gbps
    Zhang, Jianmin
    Chen, Qinghua B.
    Qiu, Kelvin
    Scogna, Antonio C.
    Schauer, Martin
    Romo, Gerardo
    Drewniak, James L.
    Orlandi, Antonio
    [J]. 2010 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC 2010), 2010, : 467 - 472
  • [2] Voltage-mode 1.5 Gbps interface circuits for chip-to-chip communication
    Lee, KJ
    Kim, TH
    Cho, UR
    Byun, HG
    Kim, S
    [J]. ETRI JOURNAL, 2005, 27 (01) : 81 - 88
  • [3] Study of the coil structure for wireless chip-to-chip communication applications
    [J]. Park, C. (pck77@ssu.ac.kr), 1600, Electromagnetics Academy (38):
  • [4] A Complete 10 Gbps Chip-to-chip Digital CMOS Silicon Photonic Link
    Zheng, Xuezhe
    Luo, Ying
    Lexau, Jon
    Liu, Frankie
    Li, Guoliang
    Thacker, Hiren
    Shubin, Ivan
    Yao, Jin
    Ho, Ron
    Cunningham, John E.
    Krishnamoorthy, Ashok V.
    [J]. 2012 CONFERENCE ON LASERS AND ELECTRO-OPTICS (CLEO), 2012,
  • [5] STUDY OF THE COIL STRUCTURE FOR WIRELESS CHIP-TO-CHIP COMMUNICATION APPLICATIONS
    Lee, Changhyun
    Park, Jonghoon
    Yoo, Jinho
    Park, Changkun
    [J]. PROGRESS IN ELECTROMAGNETICS RESEARCH LETTERS, 2013, 38 : 127 - 136
  • [6] Terahertz Band Interconnect Architecture for Future Chip-to-Chip Wireless Communication
    Elkarkraoui, Taieb
    Nezhad-Ahmadi, Mohammad-Reza
    Safavi-Naeini, Safieddin
    [J]. 2020 45TH INTERNATIONAL CONFERENCE ON INFRARED, MILLIMETER, AND TERAHERTZ WAVES (IRMMW-THZ), 2020,
  • [7] Integrated On-Chip Antennas for Chip-to-Chip Communication
    Yordanov, Hristomir H.
    Russer, Peter
    [J]. 2008 IEEE ANTENNAS AND PROPAGATION SOCIETY INTERNATIONAL SYMPOSIUM, VOLS 1-9, 2008, : 41 - 44
  • [8] A 40 GHz wireless link for chip-to-chip communication in 65 nm CMOS
    Tikka, Tero
    Viitala, Olli
    Ryynanen, Jussi
    [J]. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2015, 83 (01) : 23 - 33
  • [9] A 40 GHz wireless link for chip-to-chip communication in 65 nm CMOS
    Tero Tikka
    Olli Viitala
    Jussi Ryynänen
    [J]. Analog Integrated Circuits and Signal Processing, 2015, 83 : 23 - 33
  • [10] 20Gbps/ch Optical Interconnection between SERDES Devices over Distances from Chip-to-Chip to Rack-to-Rack
    Sakai, J.
    Noda, A.
    Yamagishi, M.
    Ohtsuka, T.
    Sunaga, K.
    Sugita, H.
    Takahashi, H.
    Oda, M.
    Ono, H.
    Yashiki, K.
    Kouta, H.
    [J]. 2008 34TH EUROPEAN CONFERENCE ON OPTICAL COMMUNICATION (ECOC), 2008,