Fault models and tests for two-port memories

被引：28
|
作者：
van de Goor, AJ [1 ]
Hamdioui, S [1 ]
机构：
[1] Delft Univ Technol, Fac Informat Technol & Syst, Dept Elect Engn, Sect Comp Architecture & Digital Technique, NL-2628 CD Delft, Netherlands
来源：
16TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 1998年
关键词：
two-port memories; memory fault models; weak faults; march tests; test length; fault coverage;
D O I：
10.1109/VTEST.1998.670898
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper the effects of simultaneous memory access on the fault modeling for two-port memories are investigated. New fault models and their march tests are presented. The obtained tests are of order O(n(2)), which makes them less practical for larger two-port memories. However, the complexity can be reduced to O(n), when the memory topology is taken into account.
引用
收藏
页码：401 / 410
页数：10
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