共 50 条
- [3] Exploring Wireless Technology for Off-Chip Memory Access 2016 IEEE 24TH ANNUAL SYMPOSIUM ON HIGH-PERFORMANCE INTERCONNECTS (HOTI), 2016, : 92 - 99
- [4] SmartShuttle: Optimizing Off-Chip Memory Accesses for Deep Learning Accelerators PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2018, : 343 - 348
- [6] Low-Power Scalable TSPI: A Modular Off-Chip Network for Edge AI Accelerators IEEE ACCESS, 2024, 12 : 141448 - 141459
- [7] Bus Width Aware Off-Chip Memory Access Minimization for CNN Accelerators 2020 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2020), 2020, : 240 - 245
- [9] Memory Bandwidth and Energy Efficiency Optimization of Deep Convolutional Neural Network Accelerators ADVANCED COMPUTER ARCHITECTURE, 2018, 908 : 15 - 29
- [10] SACC: Split and Combine Approach to Reduce the Off-chip Memory Accesses of LSTM Accelerators PROCEEDINGS OF THE 2022 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2022), 2022, : 580 - 583