System-on-a-Chip vs. System-in-a-Package: Design and interconnection issues (invited)

被引：0
|
作者：
Sakurai, T
机构：
[1] Univ Tokyo, Ctr Collaborat Res, Meguro Ku, Tokyo 1538505, Japan
[2] Univ Tokyo, Inst Ind Sci, Meguro Ku, Tokyo 1538505, Japan
来源：
ADVANCED METALLIZATION CONFERENCE 2003 (AMC 2003) | 2004年
关键词：
D O I：
暂无
中图分类号：
O646 [电化学、电解、磁化学];
学科分类号：
081704 ;
摘要：
System-in-a-Package (SiP) provides new means to implement an electronic system with the quicker turn-around-time and the lower non-recurring engineering cost (NRE) compared with System-on-a-Chip. The discussion of SoC vs. SiP should lead to a win-win relationship between SoC and SiP, not to a competing relationship. This paper describes issues in SoC including viewpoints from design and interconnection and how SiP covers SoC shortcomings.
引用
收藏
页码：3 / 9
页数：7
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