A Novel Architecture for CIC Decimation Filter

被引：0
|
作者：
Sachin, B. R. [1 ]
Ullas, B. S. [1 ]
机构：
[1] RV Coll Engn, Dept Elect & Commun, Bangalore, Karnataka, India
来源：
2014 INTERNATIONAL CONFERENCE ON ADVANCES IN ELECTRONICS, COMPUTERS AND COMMUNICATIONS (ICAECC) | 2014年
关键词：
CIC filter structure; Decimation; ModelSim; FPGA;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Cascaded Integrator Comb (CIC) structure is used extensively in the design of a decimation filter. This paper analyses the existing design of decimation filter and proposes a new design with reduced hardware requirements. The designs are modelled using VHDL, simulated using ISim and implemented in Spartan 3E FPGA. The synthesis report shows the reduction in number of I/O bits.
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页数：2
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