A novel design assistant for analog circuits

被引：5

作者：

Wolf, M ^{[1
]}

Kleine, U ^{[1
]}

Schafer, F ^{[1
]}

机构：

[1] Otto Von Guericke Univ, Inst Measurement Technol & Elect, D-39016 Magdeburg, Germany

来源：

PROCEEDINGS OF THE ASP-DAC '98 - ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE 1998 WITH EDA TECHNO FAIR '98 | 1998年

关键词：

D O I：

10.1109/ASPDAC.1998.669533

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a new design assistant for analog integrated circuits. The interactive tool is implemented in the Design Framework II of Cadence and supports the designer during circuit design. With the help of this new assistant analog designers can create ad hoc layouts of their circuits. These layouts are automatically extracted, and the updated netlist of the circuit is used for further simulation and optimization steps. Thus the optimization is speeded up and the reliability of the design is improved due to the more accurate modeling of the parasitic circuit elements. The use of the design assistant will be demonstrated by various examples.

引用

页码：495 / 500

页数：6

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