Possible Reductions to Generate circuits from BDDs

被引：1

作者：

Brandao, Eduarde D. ^{[1
]}

Nespolo, Joao P. ^{[1
]}

Peralta, Renato D. ^{[1
]}

Butzen, Paulo F. ^{[2
]}

Reis, Andre I. ^{[1
]}

机构：

[1] UFRGS Univ Fed Rio Grande do Sul, PPGC Inst Informat, Porto Alegre, RS, Brazil

[2] UFRGS Univ Fed Rio Grande do Sul, Sch Engn, Porto Alegre, RS, Brazil

来源：

2022 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2022) | 2022年

关键词：

Digital circuits; BDDs - Binary Decision Diagrams; multiplexer circuits; AIGs - And Inverter Graphs;

D O I：

10.1109/ISVLSI54635.2022.00091

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a systematic way to derive digital circuits from Binary Decision Diagrams (BDDs). It is well known that BDD nodes correspond to the Shannon decomposition, which can be implemented with a multiplexer. A multiplexer will result in three And-Inverter-Graph (AIG) nodes. However, simplifications may apply. This paper identifies eight different possible simplifications to the general multiplexer case. We demonstrate that applying these simplifications results in smaller AIGs derived from BDDs.

引用

页码：406 / 409

页数：4

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