A 17 GHz direct digital synthesizer in a InP DHBT technology

被引:0
|
作者
Zhang, Yi [1 ,2 ]
Li, Xiaopeng [1 ,3 ]
Zhang, Youtao [1 ,3 ]
Zhang, Min [1 ,3 ]
Guo, Yufeng [1 ]
Gao, Hao [4 ]
机构
[1] Nanjing Univ Posts & Telecommun, Natl & Local Joint Engn Lab, RF & Microassembly Technol, Nanjing 210023, Peoples R China
[2] Southeast Univ, State Key Lab Millimeter Waves, Nanjing 210096, Peoples R China
[3] Nanjing Elect Device Inst, Nanjing 211153, Peoples R China
[4] Eindhoven Univ Technol, POB 513, NL-5600 MB Eindhoven, Netherlands
基金
中国博士后科学基金; 中国国家自然科学基金;
关键词
DDS; InP DHBT; nonlinear DAC; phase accumulator; clock distribution; CLOCK FREQUENCY;
D O I
10.1007/s12046-021-01710-4
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Direct digital synthesizer (DDS) is an essential part of the multi-band digital phased array radar system due to its broad frequency generation ability. In this paper, a 17 GHz 8-bit ROM-less DDS in a 0.7 mu m InP double hetero-junction bipolar transistor (DHBT) technology is presented. The DDS adopts a sin-weighted nonlinear Digital-to-Analog Converter (DAC) to achieve phase-to-amplitude conversion. A simplified pipelined phase accumulator is applied, and its adder is designed according to the majority decision algorithm to reduce power consumption. The DDS is fabricated in an in-house 0.7 mu m InP DHBT technology. The measured results demonstrate that the maximum input clock frequency is 17 GHz, and it can synthesize sin-wave outputs from 66.41 MHz to 8.5 GHz in 66.41 MHz steps. The average Spurious-free dynamic range (SFDR) for the output signal of the DDS is - 18.1 dBc. The chip integrates about 1700 transistors, consumes 7.4 W, and has a Figure of merit (FOM) of 2.3 GHz/W.
引用
收藏
页数:9
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