Performance Analysis of Fractional-Order Digital Phase-Locked Loops

被引:0
|
作者
El-Khazali, R. [1 ]
Tawalbeh, N. [2 ]
Al-Khatib, O. [1 ]
AbuShawish, I. [1 ]
机构
[1] Khalifa Univ Sci Technol & Res, ECE Dept, Sharjah, U Arab Emirates
[2] Univ Jordan, Elect Engn Dept, Amman, Jordan
关键词
Phase-Locked Loop; Digital-Phase Locked Loop; Fractional-Order; Fractional Calculus; Stability; Discretization;
D O I
暂无
中图分类号
O29 [应用数学];
学科分类号
070104 ;
摘要
A new type of fractional-order digital phase-locked loops (FoDPLLs) is proposed. They comprise a fractional-order digital controlled oscillator (FoDCO) and a new form of fractional-order filters (FoF). The FoDPLLs are obtained by discretizing the continuous fractional differential operators using a closed-form solution. These operators generate biquadratic rational z-transfer functions, which yield robust and stable 4th-order FoDPLLs. This represents a significant order reduction over other discretization methods. The proposed operators reduce the design of the FoDPLLs to selecting only four parameters; the loop gain, the filter time constant, and the orders of both the FoF and the FoDCO. The performances of the analog and digital phase-locked loops are thoroughly investigated and illustrated via several numerical examples.
引用
收藏
页数:6
相关论文
共 50 条
  • [1] Fractional-order digital phase-locked loop
    El-Khazali, Reyad
    [J]. 2007 14TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-4, 2007, : 963 - 966
  • [2] NOISE PERFORMANCE OF FRACTIONAL-ORDER PHASE-LOCKED LOOP
    El-Khazali, Reyad
    Ahmad, Wajdi
    Memon, Zulfiqar A.
    [J]. ICSPC: 2007 IEEE INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND COMMUNICATIONS, VOLS 1-3, PROCEEDINGS, 2007, : 572 - +
  • [3] Fractional-order phase-locked loop
    El-Khazali, Reyad
    Ahmad, Wajdi
    [J]. 2007 9TH INTERNATIONAL SYMPOSIUM ON SIGNAL PROCESSING AND ITS APPLICATIONS, VOLS 1-3, 2007, : 1326 - +
  • [4] DIGITAL PHASE-LOCKED LOOPS
    不详
    [J]. HEWLETT-PACKARD JOURNAL, 1987, 38 (10): : 15 - 15
  • [5] Digital Phase-Locked Loops
    Levantino, Salvatore
    [J]. 2018 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2018,
  • [6] A Digital BIST for Phase-Locked Loops
    Sliech, Kevin
    Margala, Martin
    [J]. 23RD IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT-TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2008, : 134 - 142
  • [7] Advanced Digital Phase-Locked Loops
    Levantino, Salvatore
    [J]. 2013 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2013,
  • [8] ON OPTIMUM DIGITAL PHASE-LOCKED LOOPS
    GUPTA, SC
    [J]. IEEE TRANSACTIONS ON COMMUNICATION TECHNOLOGY, 1968, CO16 (02): : 340 - &
  • [9] Fractional Spur Suppression in All-Digital Phase-Locked Loops
    Chen, Peng
    Huang, XiongChuan
    Staszewski, Robert Bogdan
    [J]. 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2015, : 2565 - 2568
  • [10] Chimeras in digital phase-locked loops
    Paul, Bishwajit
    Banerjee, Tanmoy
    [J]. CHAOS, 2019, 29 (01)