Performance and error analysis of the algorithms for analog to multi-valued digital conversion

被引：0
|
作者：
Gandhi, A. S. [1 ]
Dighe, A. M.
机构：
[1] Visvesvaraya Natl Inst Technol, Dept Elect & Comp Sci, Nagpur 440011, Maharashtra, India
[2] Yeshwantrao Chavan Coll Engn, Dept Elect, Nagpur 441110, Maharashtra, India
来源：
IETE JOURNAL OF RESEARCH | 2006年 / 52卷 / 01期
关键词：
multi-valued logic; analog-to-digital conversion; successive approximation;
D O I：
10.1080/03772063.2006.11416440
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Generalised successive approximation algorithms for analog to multi-valued digital conversion with uniform quantization were published in an earlier paper by the same authors. In this paper, the information content in the output of the algorithms is determined. The results are used to derive an expression for a figure of merit of the algorithms. The figure-ofmerit is the basis of generalised implementation architectures. Also, the analysis of the behaviour of the generalised algorithms in the presence of comparison error is presented. General strategies for AID conversion error correction are developed based on the analysis results.
引用
收藏
页码：53 / 64
页数：12
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