A scalable and pipelined FPGA implementation of an OC192WF scheduler

被引：0

作者：

Merhebi, A ^{[1
]}

Mohamed, OA ^{[1
]}

机构：

[1] Concordia Univ, ECE Dept, Montreal, PQ, Canada

来源：

2004 IEEE INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY, PROCEEDINGS | 2004年

关键词：

D O I：

10.1109/FPT.2004.1393308

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we propose an FPGA implementation of a multi protocol Weighted Fair (WF) queuing algorithm able to handle variable length packets targeted for POS interfaces and ideal for the design of hybrid IP/ATM switches. Our contributions is two folds: First, we have combined the Highest Value First scheme and the Round Robin scheme into a single pipelined design able to schedule traffic for 4 channels in parallel. Second, we showed how to build higher order WF queuing system without decreasing the overall performance of our scheduler. As a result, our scheduler is general enough to accommodate ATM (UTOPIA L3/L4), POS/PL3 (OC48) as well as POS/PL4 (OC192) interfaces.

引用

页码：395 / 398

页数：4

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