System-level performance evaluation of three-dimensional integrated circuits

In this paper, the wire (interconnect)-length distribution of three-dimensional (3-D) integrated circuits (ICs) is derived using Rent's Rule and following the methodology used to estimate two-dimensional (2-D) (wire-length distribution [1]). Two limiting Eases of connectivity between logic gates on different device layers are examined by comparing the wire-length distribution and average and total wire-length. System performance metrics such as dock frequency, chip area, etc. are estimated using wire-length distribution, interconnect delay criteria, and simple models representing the cost or complexity for manufacturing 3-D ICs, The technology requirement for interconnects in 3-D integration is also discussed.