A comprehensive in-depth study of tri-state inverter based DCO

被引:1
|
作者
Terosiet, M. [1 ]
Zianbetov, E. [2 ]
Vallette, F. [3 ]
Louerat, M. M. [3 ]
Garda, P. [3 ]
Galayko, D. [3 ]
Feruglio, S. [3 ]
机构
[1] Univ Cergy Pontoise, CNRS UMR 8051, ETIS, ENSEA, F-95004 Cergy Pontoise, France
[2] Intento Design Corp, F-75001 Paris, France
[3] Sorbonne Univ, LIP6, CNRS UMR 7606, F-75005 Paris, France
来源
MICROELECTRONICS JOURNAL | 2020年 / 99卷 / 99期
关键词
CMOS; Digitally controlled ring oscillators; Jitter; PHASE-LOCKED-LOOP; OSCILLATION FREQUENCY; JITTER; NOISE; DESIGN; DELAY; MODEL; PLL;
D O I
10.1016/j.mejo.2020.104760
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper proposes an in-depth analysis of the tri-state inverter based digitally controlled oscillator. This oscillator topology has been reported in numerous publication, however its features remain poorly understood. In this study, we propose to focus on these lacks. We specifically addressed the oscillation period and the associated jitter as these quantities are the design key parameters. In this paper, we propose analytical expressions taking into consideration the design, the technology as well as the input code. These equations are suitable for hand calculations and have helped to establish a design methodology for rapid implementation. Two circuits have been designed in STMicroelectronics CMOS 65 nm process. The first one was evaluated through simulations. Then, the measurement results obtained with the second circuit manufactured within the same technology node are presented. Finally, the experimental data support the proposed theory.
引用
收藏
页数:11
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