Design of Low-Power Comparator in the Context of Big Data

Big data is supported by the greatly improved bandwidth of network and calculation. With the acceleration of the data center, the problem of power consumption and heat,. dissipation arises. According to the low energy consumption property of reversible circuits, a novel reversible comparator is proposed based on the elementary 1 bit and 2 bit reversible gates. 1 bit comparator and the cascade module are constructed based on the SAT concept according to the data transition relationship among elementary gates. The structure of n bit comparator is also put forward by modular design. The characteristics of Low quantum cost and minimum latency are guaranteed by utilizing of bounded model checking technique to get the basic building blocks. The circuits proposed can be used as the basic computing elements of other reversible circuit, and to promote the application of Big Data from the perspective of hardware development.