Parallel hardware implementation of cellular learning automata based evolutionary computing (CLA-EC) on FPGA

被引：0
|
作者：
Hariri, A [1 ]
Rastegar, R [1 ]
Zamani, MS [1 ]
Meybodi, MR [1 ]
机构：
[1] Amirkabir Univ Technol, Tehran, Iran
来源：
FCCM 2005: 13TH ANNUAL IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, PROCEEDINGS | 2005年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The CLA-EC is a model obtained by combining the concepts of cellular learning automata and evolutionary algorithms. The parallel structure of the CLA-EC makes it suitable for hardware-based applications including evolvable hardware. In this paper, based on the SIMD model, a parallel architecture is proposed and implemented on FPGA. Simulation results show that the proposed architecture can solve optimization problems thousands times faster than the sequential implementations.
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页码：311 / 313
页数：3
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