3D RRAM: DESIGN AND OPTIMIZATION

被引:0
|
作者
Kang, Jinfeng [1 ]
Gao, Bin [1 ]
Chen, B. [1 ]
Huang, P. [1 ]
Zhang, F. F. [1 ]
Deng, Y. X. [1 ]
Liu, L. F. [1 ]
Liu, X. Y. [1 ]
Chen, H-Y. [2 ]
Jiang, Z. [2 ]
Yu, S. M. [3 ]
Wong, H-S Philip [2 ]
机构
[1] Peking Univ, Inst Microelect, Beijing 100871, Peoples R China
[2] Stanford Univ, Dept Elect Engn, Stanford, CA 94305 USA
[3] Arizona State Univ, Sch Comp Informat & Decis Syst Engn, Tempe, AZ 85281 USA
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暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A novel vertical RRAM for 3D cross-point architecture is proposed. The design and optimization issues of the proposed vertical RRAM for 3D cross-point architecture array are addressed from both device and array levels. A double layer stacked HfOx based vertical RRAM devices with interface engineering fabricated using a cost-effective fabrication process. The excellent performances such as low reset current, fast switching speed, high switching endurance and disturbance immunity, good retention and self-selectivity are demonstrated in the fabricated HfOx based vertical RRAM devices. The opimized design guidances for the 3D cross-point architecture array are presented.
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页数:4
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