Modeling of NMOS Performance Gains from Edge Dislocation Stress

被引：0

作者：

Weber, Cory E. ^{[1
]}

Cea, Stephen M. ^{[1
]}

Deshpande, Hemant ^{[2
]}

Golonzka, Oleg ^{[2
]}

Liu, Mark Y. ^{[2
]}

机构：

[1] Intel Corp, Proc Technol Modeling, RA3-254,2501 NW 229th Ave, Hillsboro, OR 97124 USA

[2] Intel Corp, Portland Technol Dev, Portland, ME USA

来源：

2011 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) | 2011年

关键词：

SILICON;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Stress from edge dislocations introduced by solid phase epitaxial regrowth increases as gate pitch is scaled, reaching 1GPa at 100nm gate pitch. This scaling trend makes edge dislocations attractive for future technology nodes, as stress from epitaxial and deposited film stressors reduces as pitch is scaled (1,2). We show a gate last flow is best for maximizing the dislocation stress, and the stress varies with layout and topography. We arrive at these results by the application of the finite element method to model the dislocation stress.

引用

页数：4

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