A Single-Channel 1.25-GS/s 11-bit Pipelined ADC with Robust Floating-Powered Ring Amplifier and First-Order Gain Error Calibration

This paper proposed a robust ring amplifier (RAMP) with floating power technique for high-speed application. The proposed RAMP exhibits inherent PVT robustness due to the floating-powered CMOS resistor and configured in a twisted way for the biasing control. The transient simulation results verify the robustness of the proposed RAMP to the fluctuation of PVT. Besides, the noise filtering effect achieves a 10 dB SNDR improvement compared to the conventional RAMP within the design region. The proposed 2-stage duty cycle stabilizer (DCS) realizes a robust duty cycle. The duty cycle variation to the PVT is reduced by an order of magnitude, from 0.3% to 0.03%. By first-order gain error calibration, the verifying ADC demonstrates 59.5 dB SNDR and 73.5 dB SFDR with a Nyquist input running at 1.25 GS/s, translating into Walden and Schreier figure-of-merit (FoM) values of 29.5 fJ/conv.-step and 162.9 dB.