A 4-GS/s 6-Bit Single-Channel TDC-Assisted Hybrid ADC Featuring Power Supply Variation Adaptation for Inter-Stage Gain Error

被引：2

作者：

Liang, Hongzhi ^{[1
]}

Liu, Shubin ^{[1
]}

Ding, Ruixue ^{[1
]}

Shen, Yi ^{[1
]}

Li, Dengquan ^{[1
]}

Zhu, Zhangming ^{[1
]}

机构：

[1] Xidian Univ, Key Lab Analog Integrated Circuits & Syst, Minist Educ, Xian 710071, Peoples R China

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2024年 / 71卷 / 01期

关键词：

Analog-to-digital converter (ADC); dynamic current-source based VTC; power supply variation dynamic adaptation technique; Time-to-digital convertor (TDC); time-domain; the inter-stage gain error (IGE); TO-TIME CONVERTER; 65-NM CMOS; SAR ADC;

D O I：

10.1109/TCSII.2023.3300320

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This brief presents a 4-GS/s6-bit single-channel time-to-digital converter (TDC)-assisted analog-to-digital converter (ADC). The proposed hybrid-domain pipeline ADC adopted flash and unipolar TDC as the 1st and 2nd quantizers. By normalizing the discharge current source between the cascode-current based voltage-to-time converter (VTC) and fully differential delay cell, the overall ADC is insensitive to the power supply variation. Together with a no-resistance current reference generator, the inter-stage gain error (IGE) caused by the process, voltage and temperature (PVT) variation can be eliminated. A prototype chip has been implemented using the proposed architecture in 28-nm CMOS occupying 0.0099 mm2. The ADC shows a signal-to-noise-and-distortion ratio (SNDR) of 30.61 dB and a spurious-free dynamic range (SFDR) of 43.37 dB. It consumes 8.1 mW at Nyquist frequency with 0.9-V supply voltage. The resulting Walden figure of merit FoMW is 73.1-fJ/conversion-step. No more than 1.07-dB SNDR variations are obtained for supply voltage varying from 0.85 to 0.95 V.

引用

页码：81 / 85

页数：5

共 2 条

[1] A 12-bit 1.1GS/s Single-Channel Pipelined-SAR ADC with Adaptive Inter-stage Redundancy
Wen, Xianshan
Fu, Tao
Gui, Ping
2023 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM, RFIC, 2023, : 17 - 20
[2] A Single-Channel 1.75GS/s, 6-Bit Flash-Assisted SAR ADC with Self-Adaptive Timer and On-Chip Offset Calibration
Liao, Yu-Sian
Chen, Wei-Zen
IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC 2021), 2021,

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