Magnetic Look-Up Table (MLUT) Featuring Radiation Hardness, High Performance and Low Power

被引:0
|
作者
Lakys, Yahya [1 ,2 ]
Zhao, Weisheng [1 ,2 ]
Klein, Jacques-Olivier [1 ,2 ]
Chappert, Claude [1 ,2 ]
机构
[1] Univ Paris 11, IEF, UMR8622, Bat 425, F-91405 Orsay, France
[2] CNRS, F-91405 Orsay, France
关键词
Hybrid Design; High Reliability; MLUT; Radiation Hardness;
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Thanks to its non-volatility, high write/sense speed and small size, Magnetic Tunnel Junction (MTJ) is under investigation to be integrated in the future reconfigurable computing circuits offering higher power efficiency and performance. Another advantage of MTJ is that it provides good radiation hardness compared with other storage technologies used in reconfigurable computing circuits. In this paper, we present a design of Magnetic Look-Up-Table (MLUT) performing radiation hardness and keeping high reconfiguration/computing speed, high reliability and low power. Simulation results using an accurate model of MTJ and CMOS 130nm design kit confirm its expected performances in terms of reliability, power and speed.
引用
收藏
页码:275 / +
页数:2
相关论文
共 50 条
  • [1] Low Power Look-Up Table Topologies for FPGAs
    Subbareddy, Thadigotla Venkata
    Reddy, Bommepalli Madhava
    Upadhyay, Har Narayan
    Elamaran, V.
    2014 INTERNATIONAL CONFERENCE ON CONTROL, INSTRUMENTATION, COMMUNICATION AND COMPUTATIONAL TECHNOLOGIES (ICCICCT), 2014, : 91 - 94
  • [2] Generating a power of an operand by a table look-up and a multiplication
    Takagi, N
    13TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS, 1997, : 126 - 131
  • [3] Design, Test, and Repair of MLUT (Memristor Look-Up Table) Based Asynchronous Nanowire Reconfigurable Crossbar Architecture
    Hongal, Veeresh
    Kotikalapudi, Raghavendra
    Choi, Minsu
    IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, 2014, 4 (04) : 427 - 437
  • [4] Omitting cache look-up for high-performance, low-power microprocessors
    Inoue, K
    Moshnyaga, VG
    Murakami, K
    IEICE TRANSACTIONS ON ELECTRONICS, 2002, E85C (02): : 279 - 287
  • [5] Omitting cache look-up for high-performance, low-power microprocessors
    Inoue, Koji
    Moshnyaga, Vasily G.
    Murakami, Kazuaki
    IEICE Transactions on Electronics, 2002, E85-C (02) : 279 - 287
  • [6] Performance Analysis and Simulation of Look-up Table Predistortion Algorithm
    Qu Xiaoxu
    Lou Jingyi
    PROCEEDINGS OF THE 2015 INTERNATIONAL INDUSTRIAL INFORMATICS AND COMPUTER ENGINEERING CONFERENCE, 2015, : 1144 - 1149
  • [7] Racetrack Memory based hybrid Look-Up Table (LUT) for low power reconfigurable computing
    Huang, Kejie
    Zhao, Rong
    Lian, Yong
    JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING, 2018, 117 : 127 - 137
  • [8] An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs
    Lazzari, Cristiano
    Fernandes, Jorge
    Flores, Paulo
    Monteiro, Jose
    INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, 2011, 6448 : 84 - +
  • [9] A novel DPWM based on fully table look-up for high-frequency power conversion
    Chin, Morris Ming-Hui
    Tu, Steve Hung-Lung
    2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, 2006, : 678 - +
  • [10] A Low-Complexity and High-Performance 2D Look-Up Table for LDPC Hardware Implementation
    Chen, Jung-Chieh
    Yang, Po-Hui
    Lain, Jenn-Kaie
    Chung, Tzu-Wen
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2009, E92A (11) : 2941 - 2944