Efficient Utilization of FPGA Multipliers for Convolutional Neural Networks

Recent advances in the field of computer vision create the demand for larger and more complex architectures for Deep Convolutional Neural Networks (CNNs). As a result, computation time and memory usage become the main bottleneck in applied deep network inference, particularly in Embedded Systems implementations. Parameter quantization is often employed in these cases to minimize the detrimental effect of the aforementioned bottlenecks. In this paper, low level hardware optimizations on fixed point convolution are considered. Emphasis is given on the utilization of Digital Signal Processing Units (DSPs) as dual multipliers and on practical considerations. Three-by-three convolution kernels are formulated based on this research and are measured as case studies. The experiments show that the proper exploitation of dual multipliers can offer significant benefits to the system.