Self-Adjusting Deadtime Generator for High-Efficiency High-Voltage Switched-Mode Power Amplifiers

被引：0

作者：

Abuelnasr, Ahmed ^{[1
]}

Ali, Mohamed ^{[1
]}

Amer, Mostafa ^{[1
]}

Nabavi, Morteza ^{[1
]}

Hassan, Ahmad ^{[1
]}

Gosselin, Benoit ^{[2
]}

Savaria, Yvon ^{[1
]}

机构：

[1] Polytech Montreal, Elect Engn Dept, Montreal, PQ H3T 1J4, Canada

[2] Univ Laval Quebec, Dept Comp & Elect Engn, Quebec City, PQ G1V 0A6, Canada

来源：

2020 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2020年

基金：

加拿大自然科学与工程研究理事会;

关键词：

Deadtime Generator; Deadtime; Power Amplifiers; Switched-Mode; Class-D; High-Efficiency; Propagation Delay Mismatch; Gate Drivers; GATE DRIVER; CONVERTERS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, we propose a novel design methodology for a deadtime generator for high-efficiency power amplifiers. It consists of a two-phase non-overlapping clock circuit and level down shifters. A 3% improvement in efficiency is achieved with a maximum efficiency of 94% in a class-D power amplifier circuit. The proposed design generates a deadtime as low as 16.7ns and eliminates the problem of propagation delay mismatch between high side and low side gate drivers. The circuit is implemented in 50V AMS 0.35 mu m CMOS technology. The deadtime generator consumes 16.5 mW, while occupying a total area of 0.068 mm(2).

引用

页数：5

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