An Arithmetic Logic Unit Design Based on Reversible Logic Gates

被引：0

作者：

Guan, Zhijin ^{[1
]}

Li, Wenjuan ^{[1
]}

Ding, Weiping ^{[1
]}

Hang, Yueqin ^{[1
]}

Ni, Lihui ^{[2
]}

机构：

[1] Nantong Univ, Coll Comp Sci & Tech, Nantong, Peoples R China

[2] Nantong Univ, Coll Elec & Info, Nantong, Peoples R China

来源：

2011 IEEE PACIFIC RIM CONFERENCE ON COMMUNICATIONS, COMPUTERS AND SIGNAL PROCESSING (PACRIM) | 2011年

基金：

中国国家自然科学基金;

关键词：

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, a design constructing the Arithmetic Logic Unit(ALU) based on reversible logic gates as logic components is proposed. By using reversible logic gates instead of using traditional logic gates such as AND gates and OR gates, a reversible ALU whose function is the same as the traditional ALU is constructed. The presented reversible ALU reduces the information bits' use and loss by reusing the logic information bits logically and realizes the goal of lowering power consumption.

引用

页码：925 / 931

页数：7

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