An Energy-Efficient Voltage-Level Shifter Based on Controlling Pull-Up Network Strength

In this paper, a new energy-efficient voltage level shifter is proposed. The power (i.e., static and dynamic) and the propagation delay of the proposed structure are reduced by using an auxiliary circuit that not only charges the critical nodes entirely up to the high supply voltage V-DDH but also controls the strength of the critical PMOS transistors. In other words, since the critical nodes are charged up to V-DDH, the static power of the circuit is reduced. Moreover, the delay and dynamic power consumption of the proposed circuit are improved, because the existing contention between the pull-up and the pull-down networks is reduced. The proposed circuit is designed and simulated in a standard 180-nm CMOS process while the input voltage level, the output voltage level, and the input signal frequency are 0.4 V, 1.8 V, and 1 MHz, respectively. Post-layout simulation results confirm that the proposed architecture shows an overall delay of 7.7 ns and energy per transition of 30 fJ. Moreover, the leakage power of the proposed architecture is only 130 pW.