Fast Center Search Algorithm with Hardware implementation for Motion Estimation in HEVC Encoder

被引：0

作者：

Medhat, Ahmed ^{[1
]}

Shalaby, Ahmed ^{[1
]}

Sayed, Mohammed S. ^{[1
]}

Elsabrouty, Maha ^{[1
]}

Mehdipour, Farhad ^{[2
]}

机构：

[1] Egypt Japan Univ Sci & Technol, POB 179, Alexandria 21934, Egypt

[2] Kyushu Univ, E JUST Ctr, Sawara Ku, Fukuoka 8140001, Japan

来源：

2014 21ST IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS) | 2014年

关键词：

HEVC; motion estimation; inter prediction; sum of absolute difference (SAD) architecture; block matching;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a Fast Center Search Algorithm (FCSA) and its hardware implementation design of integer Motion Estimation for High Efficiency Video Coding (HEVC). FCSA achieves average time saving ratio up to 40% for HD video sequences with respect to full search, with insignificant loss in terms of PSNR performance and bit rate. The proposed hardware implementation shows that it meets the requirements of 30 4K frame per second with +/- 16 search window at 550 MHz. The prototyped architecture utilizes 8% of the LUTs and 4% of the slice registers in Xilinx Virtex-6 XC6VLX-550T FPGA.

引用

页码：155 / 158

页数：4

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