Very low input impedance low power current mirror

In this paper a novel low input impedance current mirror/source is proposed. The principle of its operation compared to that of the simple current mirror is discussed. Also are given the comparative simulation results with HSPICE in TSMC 0.18 mu m CMOS which verify the theoretical formulation and operation of the proposed structure. Simulation results show an input resistance for the proposed current mirror about 0.006 a"broken vertical bar. This is 4 x 10(5) times lower than that of the simple one while both working with 1.5 V supply and 50 mu A bias current. It consumes only 161 mu W and exhibits an excellent current error value of Zero at 55 mu A which remains below 0.6% up to 100 mu A. Favorably its minimum output voltage is reduced to 0.2 V.