Analysis of CMOS RF LNAS with ESD protection

被引：0
|
作者：
Chandrasekhar, V [1 ]
Mayaram, K [1 ]
机构：
[1] Oregon State Univ, Dept Elect & Comp Engn, Corvallis, OR 97331 USA
来源：
2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL IV, PROCEEDINGS | 2002年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents an analysis that accounts for the effect of standard ESD structures on critical LNA specifications of noise figure, input matching and gain. A common-source-cascode CMOS RF LNA is used for this analysis. It is shown that the ESD structures degrade LNA performance particularly for higher frequency applications. The analysis has been validated with SpectreRF simulations for a 0.25-mum CMOS process. Design techniques are also proposed for designing LNAs with ESD protection.
引用
收藏
页码：799 / 802
页数：4
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