Two Phase Clocked Adiabatic Static CMOS Logic

被引：10
|
作者：
Anuar, Nazrul [1 ]
Takahashi, Yasuhiro [2 ]
Sekine, Toshikazu [2 ]
机构：
[1] Gifu Univ, Grad Sch Engn, 1-1 Yanagido, Gifu 5011193, Japan
[2] Gifu Univ, Dept Elect & Elect Engn, Gifu 5011193, Japan
来源：
2009 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP PROCEEDINGS | 2009年
关键词：
D O I：
10.1109/SOCC.2009.5335671
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper demonstrates the low-energy operation of a two-phase clocked adiabatic static CMOS logic (2PASCL) on the basis of the results obtained in the simulation of a 4-bit ripple-carry adder (RCA) and D-flipflop employing 2PASCL circuit technology. Two-phase unsymmetrical power supply clocks are introduced to increase the logic transition level. Energy dissipation in the unsymmetrical clocked 2PASCL RCA and D-flipflop are 77.2% and 55.5% less than that in a static CMOS at transition frequencies of 10-100 MHz respectively.
引用
收藏
页码：83 / +
页数：2
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