共 50 条
- [1] AN AREA-EFFICIENT COLOR DEMOSAICKING SCHEME FOR VLSI ARCHITECTURE [J]. INTERNATIONAL JOURNAL OF INNOVATIVE COMPUTING INFORMATION AND CONTROL, 2011, 7 (04): : 1739 - 1752
- [2] Adaptable, Fast, Area-Efficient Architecture for Logarithm Approximation with Arbitrary Accuracy on FPGA [J]. JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2010, 58 (03): : 301 - 310
- [3] Adaptable, Fast, Area-Efficient Architecture for Logarithm Approximation with Arbitrary Accuracy on FPGA [J]. Journal of Signal Processing Systems, 2010, 58 : 301 - 310
- [4] A Parallel and Area-Efficient Architecture for Deblocking Filter and Adaptive Loop Filter [J]. 2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2011, : 945 - 948
- [5] Area-efficient analog VLSI architecture for state-parallel viterbi decoding [J]. Proc IEEE Int Symp Circuits Syst, (II-432 - II-435):
- [6] An area-efficient analog VLSI architecture for state-parallel Viterbi decoding [J]. ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2: ANALOG AND DIGITAL CIRCUITS, 1999, : 432 - 435
- [9] Area-efficient 2-D shift-variant convolvers for FPGA-based digital image processing [J]. 2005 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS - DESIGN AND IMPLEMENTATION (SIPS), 2005, : 209 - 213
- [10] Area-efficient parallel decoder architecture for high rate QC-LDPC codes [J]. 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 5107 - +