Implementing an Interval Type-2 Fuzzy Processor Onto a DSC 56F8013

被引：0
|
作者：
Leottau, Leonardo [1 ]
Melgarejo, Miguel [1 ]
机构：
[1] Univ Distrital Francisco Jose de Caldas, Fac Engn, Lab Automat Microelect & Computat Intelligence LA, Bogota, Colombia
来源：
2010 IEEE INTERNATIONAL CONFERENCE ON FUZZY SYSTEMS (FUZZ-IEEE 2010) | 2010年
关键词：
LOGIC; SETS;
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
This paper presents the implementation of an interval type-2 fuzzy logic processor onto a Digital Signal Controller. The implementation is carried out using the improved iterative algorithm (IASCO) for type reduction. Results show the demand of hardware resources and the computational complexity of the proposed algorithm. Besides, it is presented the influence of parameters such as speed, memory use, accuracy, and resolution in the processor performance.
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页数：4
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