Implementing interval type-2 fuzzy processors

The implementation of interval type-2 fuzzy processors (IT2-FP), which takes advantage of the parallelism in hardware realizations, is presented. It details particular considerations for the design of the different components of the architecture. The model uses four stages to compute an entire type-2 fuzzy inference, comprising singleton fuzzification, inference engine, approximated type-reduction (TR), and defuzzification. There are four stages in the architecture of the processor, comprising a fuzzification array, a rule unit array, a type-reduction circuit and an additional control unit. The control unit of the processor is a simple circuit that is in charge of synchronizing the operations and the data flow among the others parts of the processor. Several design options have been presented for implementing the different components of the processor.