Comparison of two leading algorithms for PLA test pattern generation

被引：0
|
作者：
Reilova, R
Valentin, R
Cruz, A
机构：
来源：
PROCEEDINGS OF THE 39TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III | 1996年
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中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The problem of fault test generation for programmable logic arrays (PLAs) is considered. The physical device faults are viewed in terms of their effect on the logical changes of the product terms constituting the PLA. Of the four possible logical faults: growth, shrinkage, appearance and disappearance; growth fault detection and test generation are investigated. The Bose and PLAtano algorithms for generating tile single-fault growth test vectors are evaluated for efficiency, generality of solution, and case of implementation.
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页码：299 / 302
页数：4
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