Optimization of Convolutional Neural Networks on Resource Constrained Devices

被引：11
|
作者：
Arish, S. [1 ]
Sinha, Sharad [2 ]
Smitha, K. G. [1 ]
机构：
[1] Nanyang Technol Univ, 50 Nanyang Ave, Singapore, Singapore
[2] Indian Inst Technol Goa, Ponda, India
来源：
2019 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2019) | 2019年
关键词：
FPGA; convolutional neural networks; hardware optimization; resource constrained devices;
D O I：
10.1109/ISVLSI.2019.00013
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Implementation of convolutional neural networks (CNNs) on resource constrained devices like FPGA (example: Zynq) etc. is important for intelligence in edge computing. This paper presents and discusses different hardware optimization methods that were employed to design a CNN model that is amenable to such devices, in general. Adaptive processing, exploitation of parallelism etc. are employed to show the superior performance of proposed methods over state of the art.
引用
收藏
页码：19 / 24
页数：6
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