Comparison for Performance and Reliability Between Nanowire FET and FinFET versus Technology Node

被引:1
|
作者
Kim, Hyunsuk [1 ,2 ]
Seo, Youngsoo [1 ,2 ]
Myong, Il Ho [1 ,2 ]
Kim, Minsoo [1 ,2 ]
Kang, Myounggon [3 ]
Shin, Hyungcheol [1 ,2 ]
机构
[1] Seoul Natl Univ, ISRC, Seoul 151744, South Korea
[2] Seoul Natl Univ, Sch Elect Engn & Comp Sci, Seoul 151744, South Korea
[3] Korea Natl Univ Transportat, Dept Elect Engn, Chungju City 380702, South Korea
关键词
FinFET; Nanowire FET (NWFET); Technology Node; Work Function Variation (WFV); Line Edge Roughness (LER); Drain-Induced-Barrier-Lowering (DIBL); MOSFETS; SOI;
D O I
10.1166/jnn.2017.14712
中图分类号
O6 [化学];
学科分类号
0703 ;
摘要
To satisfy requirements especially for future devices, studies of Nanowire FET (NWFET) and FinFET is highly motivated in many groups. This is because NWFET and FinFET have strong gate controllability, allowing them to maintain great performance compared with that of conventional planar MOSFETs. Therefore, the limiting factors affecting the performance and/or reliability for each device should be considered carefully. In this work, our group chose various perspectives to evaluate FinFET and NWFET in technology nodes. The results from the selected factors according to technology nodes were analyzed by TCAD simulation. By observing the simulation results versus the technology node, a guideline for proper device properties according to the technology node was proposed. Our group found that the NWFET as a future device has advantages in terms of performance. However, it is found that FinFET can be more advantageous than NWFET in terms of reliability.
引用
收藏
页码:7227 / 7230
页数:4
相关论文
共 50 条
  • [1] FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability
    Nagy, Daniel
    Indalecio, Guillermo
    Garcia-Loureiro, Antonio J.
    Elmessary, Muhammad A.
    Kalna, Karol
    Seoane, Natalia
    IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2018, 6 (01): : 332 - 340
  • [2] Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes
    Nagy, Daniel
    Espineira, Gabriel
    Indalecio, Guillermo
    Garcia-Loureiro, Antonio J.
    Kalna, Karol
    Seoane, Natalia
    IEEE ACCESS, 2020, 8 : 53196 - 53202
  • [3] Performance & Reliability of 3D Architectures (&UPI;fet, Finfet, Ωfet)
    Laurent, A.
    Garros, X.
    Barraud, S.
    Pelloux-Prayer, J.
    Casse, M.
    Gaillard, F.
    Federspiel, X.
    Roy, D.
    Vincent, E.
    Ghibaudo, G.
    2018 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2018,
  • [4] Comparison of Various Factors Affected TID Tolerance in FinFET and Nanowire FET
    Won, Hyeonjae
    Ham, Ilsik
    Jeong, Youngseok
    Kang, Myounggon
    APPLIED SCIENCES-BASEL, 2019, 9 (15):
  • [5] BTI Lifetime Reliability of Planar MOSFET Versus FinFET for 16 nm Technology Node
    Mahmoud, Mohamed Mounir
    Soin, Norhayati
    PROCEEDINGS OF THE 2016 IEEE 23RD INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA), 2016, : 262 - 266
  • [6] FinFET Evolution Toward Stacked-Nanowire FET for CMOS Technology Scaling
    Zheng, Peng
    Connelly, Daniel
    Ding, Fei
    Liu, Tsu-Jae King
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2015, 62 (12) : 3945 - 3950
  • [7] Comparison of work function variation between FinFET and 3D stacked nanowire FET devices for 6-T SRAM reliability
    Ko, Kyul
    Son, Dokyun
    Kang, Myounggon
    Shin, Hyungcheol
    SOLID-STATE ELECTRONICS, 2018, 140 : 74 - 79
  • [8] Performance Evaluation of FinFET and Nanowire at Different technology nodes
    Hajare, Raju
    Lakshminarayana, C.
    Raghunandan, Cyril Prasanmaj G. H.
    Hegde, Yogesh
    2015 INTERNATIONAL CONFERENCE ON EMERGING RESEARCH IN ELECTRONICS, COMPUTER SCIENCE AND TECHNOLOGY (ICERECT), 2015, : 114 - 119
  • [9] Performance Comparison of Junctionless FinFET with Nanosheet FET and Device Design Guidelines
    Saini, Sonia
    Saini, Gaurav
    INDIAN JOURNAL OF PURE & APPLIED PHYSICS, 2024, 62 (06) : 490 - 502
  • [10] Comparison of Temperature Dependent Carrier Transport in FinFET and Gate-All-Around Nanowire FET
    Kim, Soohyun
    Kim, Jungchun
    Jang, Doyoung
    Ritzenthaler, Romain
    Parvais, Bertrand
    Mitard, Jerome
    Mertens, Hans
    Chiarella, Thomas
    Horiguchi, Naoto
    Lee, Jae Woo
    APPLIED SCIENCES-BASEL, 2020, 10 (08):