Novel input ESD protection circuit with substrate-triggering technique in a 0.25-μm shallow-trench-isolation CMOS technology

被引：0

作者：

Ker, MD ^{[1
]}

Chen, TY ^{[1
]}

Wu, CY ^{[1
]}

Tang, H ^{[1
]}

Su, KC ^{[1
]}

Sun, SW ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Inst Elect, Integrated Circuits & Syst Lab, Hsinchu 30039, Taiwan

来源：

ISCAS '98 - PROCEEDINGS OF THE 1998 INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-6 | 1998年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

A substrate-triggering technique, to increase the ESD robustness and to reduce the trigger voltage of the ESD protection device, is proposed to improve the ESD-protection efficiency of the input ESD protection circuit in deep-submicron CMOS technology. Through suitable substrate-triggering design on the device structure, this proposed input ESD protection circuit can successfully protect the thinner gate oxide (50 Angstrom) of the input stage in a 0.25-mu m CMOS technology and sustain an ESD level above 2000V without extra process modification.

引用

页码：A212 / A215

页数：4

共 5 条

[1] CMOS on-chip ESD protection design with substrate-triggering technique
Industrial Technology Research Inst, Hsinchu, Taiwan
Proc IEEE Int Conf Electron Circuits Syst, (273-276):
[2] Compact layout rule extraction for latchup prevention in a 0.25-μm shallow-trench-isolation silicided bulk CMOS process
Ker, MD
Lo, WY
Chen, TY
Tang, H
Chen, SS
Wang, MC
INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS, 2001, : 267 - 272
[3] A novel 0.25 mu m shallow trench isolation technology
Chen, C
Chou, JW
Lur, W
Sun, SW
IEDM - INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST 1996, 1996, : 837 - 840
[4] MOS-bounded diodes for on-chip ESD protection in a 0.15-μm shallow-trench-isolation salicided CMOS process
Ker, MD
Lin, KH
Chuang, CH
2003 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, PROCEEDINGS OF TECHNICAL PAPERS, 2003, : 84 - 87
[5] Critical dimension control optimization methodology on shallow trench isolation substrate for sub-0.25 μm technology gate patterning
Fan, MH
Gerung, H
Yelehanka, PR
Cheng, A
Zhou, MS
Chi, C
Tan, CH
Xie, J
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 2001, 19 (02): : 456 - 460

← 1 →