Design on micro power dissipation E/D NMOS reference source

In this study, a novel micro power dissipation E/D NMOS reference source circuit was presented. The circuit is simple in structure, but is practical. Compared with a traditional BiCMOS band-gap reference source, the micro power dissipation E/D NMOS reference source has a small static current, and eliminates the need of parasitic bipolar transistor and resistor. All you need to do is to add a depletion-mode N-MONFET process to a conventional P-well process technology. An E/D NMOS reference source circuit has been developed in 2 mu in silicon-gate self-aligned CMOS process technology. In the range -55 to 125 degrees C, the static current measured was less than 2 mu A, the voltage regulation measured was less than 2mV, and the temperature coefficient measured was less than 100ppm/degrees C.