Reconfigurable Ultra Wideband Radio Receiver

Wireless Sensor Network (WSN) applications demand ultra low power devices. Digital Ultra Wideband (UWB) transceiver can be used as the communication module in a WSN due it its potential for location tracking, ranging and low data rate communication. Current digital UWB receiver architecture incorporates heavy parallelism, which significantly increases power consumption, especially during the acquisition and synchronisation (AS) mode. Analysis shows that real time reconfigurability for the digital backend of the UWB receiver has the potential to reduce the average power consumption. This paper proposes a novel real time reconfigurability algorithm (RTRA) which reduces the power consumption by switching off the unwanted parallel blocks during the AS mode. It consists of estimation, translation and a control block. An FPGA implementation showed that an average power saving of approximately 30% can be achieved by the proposed RTRA over a normal receiver.