CMOS Instrumentation Amplifier Design with 180nM Technology

被引：0

作者：

Gupta, Gaytri ^{[1
]}

Tripathy, Mr. ^{[1
]}

机构：

[1] AMITY Univ, Dept ECE, Sect 125, Noida, India

来源：

2014 IEEE INTERNATIONAL CONFERENCE ON CIRCUIT, POWER AND COMPUTING TECHNOLOGIES (ICCPCT-2014) | 2014年

关键词：

DC offset; OTA; Instrumentation Amplifier; CMRR; PSRR;

D O I：

暂无

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

This paper description of the design technique of Instrumentation Amplifier used in biomedical appliances. This Instrumentation amplifier is designed with the combination of Operational Tranconductance amplifier (OTA). We have used the Operational Tranconductance amplifier due to its high input impedance, low output impedance, low DC offset, low noise, high common mode rejection ratio (CMRR) and high power supply rejection ratio (PSRR). The circuit has been designed with the Cadence Virtusoo Software with 180 nM technology. The main features of this OTA are 20.13 dB open loop gain with a 0.23 KHz bandwidth, 124 dB CMRR, 65 dB PSRR and offset voltage is 0.3mV DC. The integrated CMOS amplifier operates to 1V power supply. The design and Simulation of this IA is completed using CADENCE Spectre with UMC 0.18 mu m technology. The power dissipation of this instrumentation amplifier is 0.50 mW.

引用

页码：1114 / 1116

页数：3

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