Effect of Back Gate on Parasitic Bipolar Effect in FD SOI MOSFETs

被引:0
|
作者
Liu, Fanyu [1 ]
Ionica, Irina [1 ]
Bawedin, Maryline [2 ]
Cristoloveanu, Sorin [1 ]
机构
[1] MINATEC, IMEP LAHC, F-38016 Grenoble, France
[2] Univ Montpellier 2, F-34095 Montpellier, France
关键词
parasitic bipolar effect; back gate; FD SOI; band-to-band tunneling; ENHANCEMENT;
D O I
暂无
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
In short-channel fully-depleted (FD) silicon-on-insulator (SOI) MOSFETs, the drain leakage current is enhanced by the parasitic bipolar transistor. The parasitic bipolar effect is induced by band-to-band tunneling and floating-body effects. It strongly depends on film thickness and back-gate voltage. We show experimentally the possibility to reduce the parasitic bipolar effect by biasing the back gate (ground plane). Based on devices simulations, we discuss the origin of the bipolar action, its suppression and the possible applications.
引用
收藏
页数:2
相关论文
共 50 条
  • [1] Extraction of the Parasitic Bipolar Gain Using the Back-Gate in Ultrathin FD SOI MOSFETs
    Liu, Fanyu
    Ionica, Irina
    Bawedin, Maryline
    Cristoloveanu, Sorin
    [J]. IEEE ELECTRON DEVICE LETTERS, 2015, 36 (02) : 96 - 98
  • [2] Parasitic bipolar effect in ultra-thin FD SOI MOSFETs
    Liu, F. Y.
    Ionica, I.
    Bawedin, M.
    Cristoloveanu, S.
    [J]. SOLID-STATE ELECTRONICS, 2015, 112 : 29 - 36
  • [3] Effect of parasitic elements on UTBB FD SOI MOSFETs RF figures of merit
    Arshad, M. K. Md
    Kilchytska, V.
    Emam, M.
    Andrieu, F.
    Flandre, D.
    Raskin, J. -P.
    [J]. SOLID-STATE ELECTRONICS, 2014, 97 : 38 - 44
  • [4] Impact of back-gate bias on the hysteresis effect in partially depleted SOI MOSFETs
    Luo Jie-Xin
    Chen Jing
    Zhou Jian-Hua
    Wu Qing-Qing
    Chai Zhan
    Yu Tao
    Wang Xi
    [J]. CHINESE PHYSICS B, 2012, 21 (05)
  • [5] Novel back-gate kink effect in SOI MOSFETs during ionizing irradiation
    Department of Physics Science and Technology, Zhongnan University, Changsha 410083, China
    不详
    不详
    [J]. Pan Tao Ti Hsueh Pao, 2008, 1 (149-152):
  • [6] Impact of back-gate bias on the hysteresis effect in partially depleted SOI MOSFETs
    罗杰馨
    陈静
    周建华
    伍青青
    柴展
    余涛
    王曦
    [J]. Chinese Physics B, 2012, 21 (05) : 477 - 482
  • [7] Substrate bias effect linked to parasitic series resistance in multiple-gate SOI MOSFETs
    Rudenko, Tamara
    Kilchytska, Valeria
    Collaert, Nadine
    Jurczak, Malgorzata
    Nazarov, Alexey
    Flandre, Denis
    [J]. IEEE ELECTRON DEVICE LETTERS, 2007, 28 (09) : 834 - 836
  • [8] On the gate capacitance limits of nanoscale DG and FD SOI MOSFETs
    Ge, LX
    Gámiz, F
    Workman, GO
    Veeraraghavan, S
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (04) : 753 - 758
  • [9] Back-Gate Lumped Resistance Effect on AC Characteristics of FD-SOI MOSFET
    Vanbrabant, Martin
    Nyssens, Lucas
    Kilchytska, Valeriya
    Raskin, Jean-Pierre
    [J]. IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, 2022, 32 (06) : 704 - 707
  • [10] Corner effect in multiple-gate SOI MOSFETs
    Xiong, W
    Park, JW
    Colinge, JP
    [J]. 2003 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2003, : 111 - 113