Power-delay optimization in MCML tapered buffers

被引：1

作者：

Alioto, Massimo ^{[1
]}

Palumbo, Gaetano ^{[2
]}

机构：

[1] Univ Siena, Dept Informat Engn, Via Laterina 8, I-53100 Siena, Italy

[2] Catania Univ, Dept Elect Elect & Syst Engn, Catania, Italy

来源：

PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10 | 2008年

关键词：

D O I：

10.1109/ISCAS.2008.4541374

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, MOS Current Mode Logic (MCML) tapered buffers are discussed from a design point of view. Closed-form design equations that relate the overall speed performance and the power consumption of MCML tapered buffers are derived for nanometer CMOS technologies, i.e. by accounting for Deep-Sub-Micron (DSM) effects from the beginning. The power-delay design space is then analytically explored, and design criteria are derived to properly size the number of stages and the current tapering factor under a speed/power constraint. The design criteria are simple enough to be used in pencil-and-paper calculations, as well as general and independent of the adopted technology. Hence, the proposed strategy provides the designer with an insight into the power-delay trade-off of MCML tapered buffers. Results are validated by means of simulations on a 90-nm CMOS technology.

引用

页码：141 / +

页数：2

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