Design and VLSI implementation of CSD filter for pre-processing of image signals

In this paper, we investigate the design and VLSI implementation of CSD (canonic signed digit) coefficient filters for high speed digital filtering. First, CSD coefficient filters are designed, which can be used as format conversion filters in place of the ones employed for the MPEGZ TM5 (test model 5). It is shown that the proposed CSD filters perform better than the conventional one, while having lower hardware complexity. Second, the pipelined bit-serial and bit-parallel architectures for the CSD filter are proposed and verified through the VHDL simulation.