A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare core

Reliability is a significant strategy concern for modern day multi-core embedded systems. On chip communicating systems are vulnerable to permanent network faults and transient faults which might essentially affect the performance of the system. Targeting at fault tolerance solution for cores with faults in Network on Chip (NoC), this paper proposes an energy-efficient fault tolerant NoC architecture using spare core. The proposed strategy comprises of finding smallest rectangular region to place the given application using a heuristic technique, and mapping vertices within the selected region, and selecting a region which results maximum overall performance and minimum communication energy. Spare core is placed within a region and connected to the vertices. Many application core graphs are used to evaluate the proposed technique. The simulation outcomes of many fault injection tests indicate that the proposed technique results in performance enhancement while also saving communication energy.