Evaluation of successive CPUs/APUs/GPUs based on an OpenCL finite difference stencil

被引:4
|
作者
Calandra, Henri [2 ]
Dolbeau, Romain [3 ]
Fortin, Pierre [1 ]
Lamotte, Jean-Luc [1 ]
Said, Issam [1 ]
机构
[1] Univ Paris 06, UPMC, CNRS, LIP6,UMR7606, 4 Pl Jussieu, F-75252 Paris 05, France
[2] Total, F-64000 Pau, France
[3] CAPS Entreprise, F-35000 Rennes, France
关键词
APU; GPU; finite difference stencil; PCI Express bus; high performance scientific computing;
D O I
10.1109/PDP.2013.65
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
The AMD APU (Accelerated Processing Unit) architecture, which combines CPU and GPU cores on the same die, is promising for GPU applications which performance is bottlenecked by the low PCI Express communication rate. However the first APU generations still have different CPU and GPU memory partitions. Currently, the APU integrated GPUs are also less powerful than discrete GPUs. In this paper we therefore investigate the interest of APUs for scientific computing by evaluating and comparing the performance of two successive AMD APUs (family codename Llano and Trinity), two successive discrete GPUs (chip codename Cayman and Tahiti) and one hexa-core AMD CPU. For this purpose, we rely on a 3D finite difference stencil, that is optimized and tuned in OpenCL. We detail the most interesting optimizations for each architecture and show very good performance in OpenCL: up to 500 Gflops on Tahiti. Finally, our results show that APU integrated GPUs outperform CPUs, and that integrated GPUs of upcoming APUs may match discrete GPUs for problems with high communication requirements.
引用
收藏
页码:405 / 409
页数:5
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