Effect of device layout on the thermal resistance of high-power thermally-shunted heterojunction bipolar transistors

被引：0

作者：

Dettmer, R ^{[1
]}

Jenkins, T ^{[1
]}

Barrette, J ^{[1
]}

Bozada, C ^{[1
]}

DeSalvo, G ^{[1
]}

Ebel, J ^{[1
]}

Gillespie, J ^{[1
]}

Havasy, C ^{[1
]}

Ito, C ^{[1
]}

Nakano, K ^{[1
]}

Pettiford, C ^{[1
]}

Quach, T ^{[1
]}

Sewell, J ^{[1
]}

Via, D ^{[1
]}

Anholt, R ^{[1
]}

机构：

[1] WRIGHT LAB,SOLID STATE SCI DIRECTORATE,WRIGHT PATTERSON AFB,OH 45433

来源：

1996 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, VOLS 1-3 | 1996年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：1607 / 1610

页数：4

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