Fast and power-efficient CMOS subranging ADCs

被引:0
|
作者
van der Goes, F. M. L.
Mulder, J.
Ward, C. M.
Lin, C. -H.
Kruse, D.
Westra, J. R.
Lugthart, M.
Arslan, E.
Bajdechi, O.
van de Plassche, R. J.
Bult, K.
机构
关键词
D O I
10.1007/1-4020-5186-7_4
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a two-step subranging ADC architecture based on interpolation, averaging, offset compensation and pipelining techniques. Application of these techniques results in fast and power-efficient converters with all accuracy between 8b and 12b.
引用
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页码:53 / 71
页数:19
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